Reducing Development Time in Thermal Imaging FPGAs
An imaging systems developer accelerated the implementation of advanced thermal imaging filters and algorithms on FPGA hardware.
Raw image (left) and image after applying filter developed with HDL Coder (right). Image: MathWorks
FLIR Systems, Wilsonville, Ore., designs, manufactures, and markets thermal imaging infrared cameras used in commercial security, firefighting, gas leak detection, and test and measurement. In a market where time and cost efficiency are key, the company seeks ways to accelerate the implementation of advanced thermal imaging algorithms on field-programmable gate array (FPGA) hardware.
FLIR needed a workflow that would speed the pace of converting a signal processing concept into an algorithm that runs in real time, on a production camera. Algorithm engineers would spend time developing an idea, only to turn the project over to a hardware engineer who would convert the algorithm into HDL code and create an FPGA implementation. The process took weeks; and when bugs were detected, it was difficult to determine if the errors were due to FPGA implementation or the algorithm.
FLIR turned to MATLAB to develop, simulate, and evaluate algorithms and HDL Coder to automate the implementation of the best algorithms on FPGAs. Using these tools, FLIR engineers established a new workflow for developing FPGA-based thermal imaging algorithms. Because the algorithm engineers are now producing FPGA prototypes themselves, they are able to take a new idea into a real-time-capable hardware prototype in just a few weeks.
The new workflow has also enabled FLIR to not only share early prototype algorithms with customers, but also show the algorithm working on FPGA hardware. In the past, customers were rarely shown simulations, because implementing these algorithms in FPGAs was a lengthy and laborious process. In one recent instance, FLIR’s manager of image processing technology showed a key customer some simulations of the most complex digital filter FLIR had ever developed. A few months later, the customer was thrilled to receive the first working camera with the latest filter. The digital filter, generated using HDL Coder, performed exactly as it was simulated in MATLAB.
FLIR algorithm engineers use this MATLAB to HDL workflow to produce better FPGA implementation; because they are intimately familiar with the design intent, they can make the right tradeoffs during the design optimization phase. Furthermore, they can quickly regenerate HDL code as needed to satisfy new requirements. Previously, they would need to ask the hardware designers to make manual edits to HDL code.
With this new workflow, the step of translating algorithms to HDL by hand has been eliminated. As a result, FLIR has cut prototyping time by as much as 60%.
In a typical project using FLIR’s new process, algorithm engineers identify new algorithms based on morphological operations and multidimensional image filtering. Specific algorithms are then selected and the algorithmic components are identified. These components are mapped to the target FPGA hardware. While the partitioning process takes place, the team replaces the high-level functions with MATLAB code that is suitable for hardware implementation and HDL code generation.
To enable bit-true simulation and analysis, engineers employ HDL Coder to automatically convert floating-point MATLAB code into fixed-point MATLAB code that is used to generate synthesizable HDL code for FPGA implementation. With this method, they can quickly verify results from the FPGA implementation against the simulated results from the original fixed-point algorithm.