2009 R&D 100 Winner
The manufacturing of copper interconnect structures in semiconductors is a high-precision process that represents 25 to 35 steps and amounts to nearly 10% of total chip manufacturing costs, or about $10 billion in market size. Despite the value, current chemical/mechanical polishing methods for these interconnects are non-quantized and often require the optimization of 20 variables. This creates the need for expensive, sophisticated equipment. A simpler way of achieving results is offered by Sinmat Inc., Gainesville, Fla., which has developed Ultra-High Precision Digital Polishing Process for Copper Interconnect Manufacturing (DCMP) that brings high-uniformity, high-planarity removal of materials used in 300/450-mm semiconductor wafer fabrication. The DCMP process features new chemistries that form a soft layer on the working surface that is easily removable under low mechanical stress (which makes it suitable for fragile low-k materials). “Digital” refers to the ability to determine the exact amount of material removal. This is aided by the ability of DCMP to minimize the effects of wafer bow, bevel, and edge. This suppresses variation of material removal rates across the wafer. Sinmat estimates that the complete adoption of its UHP process will increase device yield for the typical manufacturer by at least 50% and decrease total cost of ownership by 80%.
Technology
Process for copper interconnect manufacturing
Developer
Sinmat Inc.