Tuesday, September 27, 2005
Yuegang Zhao
Lead Applications Engineer
Keithley Instruments, Inc. Cleveland, Ohio
BS, Physics, Peking Univ., Beijing, China, MS, Semiconductor Physics, Univ. of Wisconsin-Madison, MBA, Whetherhead School of Management, Case Western Reserve Univ., Cleveland
Published technical papers (10+)
U.S. Patent Author (2)
Web seminar host (3) |
The continuing shrinking of semiconductor features results in correspondingly smaller currents and voltages. These effects demand that new measurement techniques, beyond traditional DC source measurements, are developed. And when device developers look to make really small current and voltage (IV) measurements in new semiconductor circuits, one of the companies that they may consider first is Keithley Instruments, Cleveland, Ohio, which has a long history (50+ yr) of developing instruments for characterizing extremely small electronic measurements. And within Keithley, Yuegang Zhao has become known as the leader in IV measurements, and in particular a technique termed pulsed stress testing.
A case in point involves on-going research in the characterization of high-k gate materials. High-k materials have a high dielectric constant, allowing them to be made thicker than SiO2 (silicon dioxide) insulators while having the same gate capacitance. Typical materials being evaluated for high-k include HfO2 (hafnium oxide), ZrO2 (zirconium oxide), Al2O3 (alumina), and their silicates.
High-k materials are used in new ultra-thin device circuits to reduce leakage currents associated with traditional materials. But, while high-k materials solve one problem, they can induce measurement errors with trap charges into the high-k characterization. Trapped charges occur when the transistor is turned on and channel carriers accumulate in the dielectric due to the vertical electric field. These charges may then cause a shift in the transistor's threshold voltage.
But, how do you measure this highly transient trapped charge so you can fix it or at least minimize it? One way, according to Zhao, is to use a double sweep in DC IV or high-frequency CV (capacitance-voltage) measurements where the presence of a hysteresis on the IV or CV curves will reveal the presence of trapping in the device. Unfortunately, in these tests, the hysteresis on an IV test is often different than that on a CV test, due to the different times required for each test.
Zhao’s work on devices, such as the Model 4200 SCS, will enable users to test for transistor threshold voltage.
Click here to enlarge |
Another test is to use a DC stress to intentionally inject charges into the gate and then use the CV or IV method to measure the threshold voltage. However, this method may underestimate the charge trapping.
Zhao's solution, on which he worked closely with engineers at SEMATECH, is to take the time scale out of the measurement process of a highly transient effect. This method employs a single pulse technique. One variation of this uses high bandwidth with resultant faster pulses (tens of nsec). In this method, the bulk traps in the high-k layer don't have the time to respond, resulting in an "intrinsic" transistor response with negligible charge-trapping.
This technique was the basis for Keithley's recently introduced Model 4200 SCS Semiconductor characterization system.
Zhao has found that the pulsed voltage techniques also provide additional information on the interface and reliability properties of high-k films. A pulsed stress test provides a method that mimics the actual stresses seen in the in-circuit devices, which provide the reliability data.
Zhao enjoys the challenge of working with the need to solve these types of emerging measurement techniques. "Keithley provides freedom to work on these problems, and there are a lot of people within the company on which to collaborate," he says. It's an exciting area for Zhao. "Even the trends change," he says. "Keeping up with those trends is the real challenge."
—Tim Studt